For increasing the response speed of the semiconductor device and reducing the power consumption, the use of a semiconductor material having high carrier mobility is a way to achieve the both functions. The semiconductor material having high carrier mobility includes for example germanium (Ge), alloy semiconductor material or compound semiconductor material. However, in a case that a semiconductor structure layer with a material different from a semiconductor substrate is stacked on the semiconductor substrate, some problems may occur. For example, the lattice size difference between the semiconductor substrate and the overlying semiconductor structure layer with the different material may cause dislocations in the semiconductor device. Due to the dislocations, the performance of the semiconductor device is deteriorated.
Conventionally, in order to fabricate a germanium-based semiconductor device including a silicon substrate, a thicker buffer layer or sacrificial layer (e.g. a silicon/germanium buffer layer) is formed on the silicon substrate, then a germanium epitaxial layer is grown on the silicon/germanium buffer layer, and then an anisotropic etching process and an isotropic etching process are sequentially performed to remove a part of the buffer layer and retain the germanium epitaxial layer.
Generally, in a case that the major material of the active region of a MOSFET is germanium, the MOSFET is referred as a germanium MOSFET. FIGS. 1A˜1H schematically illustrate a partial process flow of fabricating a conventional germanium MOSFET.
Firstly, please refer to the cross-sectional view as shown in FIG. 1A. A silicon/germanium buffer layer 110, a germanium epitaxial layer 120 and a mask layer 130 are sequentially formed on a silicon substrate 100.
Next, please refer to the top view as shown in FIG. 1B. The mask layer 130 is patterned to expose a part of the germanium epitaxial layer 120. FIG. 1C is a schematic cross-sectional view illustrating the structure of FIG. 1B and taken along the line AA′. As shown in FIG. 1C, the silicon/germanium buffer layer 110, the germanium epitaxial layer 120 and the patterned mask layer 130 are sequentially formed on the silicon substrate 100.
Next, please refer to the cross-sectional view as shown in FIG. 1D. An anisotropic etching process is performed to remove an exposed part of the germanium epitaxial layer 120 by using the silicon/germanium buffer layer 110 as an etch stop layer. Consequently, a channel region 122 is formed.
Next, please refer to the cross-sectional view as shown in FIG. 1E. A protecting layer 140 is formed over the remaining germanium epitaxial layer 120 to protect the sidewall of the channel region 122. Then, an isotropic etching process is performed to remove the silicon/germanium buffer layer 110 between the silicon substrate 100 and the channel region 122. Consequently, the channel region 122 is floated over the silicon substrate 100.
Next, please refer to the cross-sectional view as shown in FIG. 1F. After the protecting layer 140 and the patterned mask layer 130 are removed, an active region 120a of the germanium MOSFET is formed in the remaining germanium epitaxial layer 120. The active region 120a is divided into a source region 121, the channel region 122 and a drain region 123. FIG. 1G is a schematic cross-sectional view illustrating the structure of FIG. 1F and taken along the line AA′. As shown in FIG. 1G, the channel region 122 is floated over the surface of the silicon substrate 100. FIG. 1H is a schematic cross-sectional view illustrating the structure of FIG. 1F and taken along the line BB′. As shown in FIG. 1H, the source region 121 and the drain region 123 are bonded on the surface of the remaining silicon/germanium buffer layer 110, and the channel region 122 is floated over the surface of the silicon substrate 10 and connected with the source region 121 and the drain region 123.
Although the semiconductor structure layer with the different material can be stacked on the semiconductor substrate to fabricate a semiconductor device, the above method of fabricating the semiconductor device is complicated. Moreover, the above fabricating method fails to effectively eliminate the dislocations (not shown) in the semiconductor device.
Therefore, there is a need of providing an approach to eliminate the above drawbacks.